This invention relates to an improvement in semiconductor memory devices with a redundant configuration to electrically provide a corrective for defective bits.
The storage capacity of semiconductor memory devices has been increased. The number of components per memory chip has been increased. The area of the memory chip has been increased. If only defect-free memory chips are selectively used, this presents a disadvantage to manufacturing costs. This calls for a corrective technique with respect to a defective bit. It is known that a semiconductor memory device employs therein a redundant configuration in which besides a primary memory cell a spare memory cell is provided so that the spare memory cell will take over from the primary memory cell in the event of failure. Following the fabrication of the semiconductor memory device, primary memory cells are first checked for possible defect. Then, if a defective primary memory cell is found, it is replaced by a spare memory cell. Thus, storage capacitance to be achieved is satisfied.
A semiconductor memory device incorporating therein the foregoing redundant configuration is known from Japanese Patent Application, published under No. 1-112598. In accordance with this semiconductor memory device, primary memory cells and spare memory cells (i.e., defect corrective memory cells) are organized in a matrix structure to form a memory cell array, and the primary memory cells are interconnected through word lines and bit lines while on the other the spare memory cells are connected together either with word lines or with bit lines, or with both the word and bit lines. The address of a defective primary memory cell is replaced by the address of a spare memory cell so that the defective memory cell is corrected. Japanese Patent Application, published under No. 62-125598, discloses a technique in which a first decoder circuit to select primary memory cells and a second decoder circuit to select spare memory cells are provided. The first decoder circuit is so organized that a plurality of logical circuits of current switching type are longitudinally stacked. During the defect corrective, a non-selective pulse voltage and a selective pulse voltage are applied to the first decoder circuit and the second decoder circuit respectively, making a defective primary memory cell non-selective and a spare memory cell selective at the same time. Additionally, U.S. Pat. No. 4,860,260, JP Patent Application, published under No. 2-113490, and JP Patent Application, published under No. 57-111893 disclose semiconductor memory devices incorporating a redundant configuration.
FIG. 9 illustrates a typical redundant configuration incorporated in the above-described conventional semiconductor memory device. Such a redundant configuration contains a sense amplifier array 1, a spare memory cell array 2, a primary (main) memory cell array 3, a primary row decoder 4A, a spare row decoder 4B, a row predecoder 5, a redundancy-use decision circuit 20, comprised of elements SD0 to SDn to store the addresses of defective memory cells and to decide whether an input address corresponds to the stored address, a column decoder 6, a data I/O buffer 7, and word lines WL0 to WLm of the primary memory cell array 3. Spare word lines of the spare memory cell array 2, indicated by SW0 to SWn, are selected by a signal from the redundancy-use decision circuit 20.
FIG. 10 shows how the primary row decoder 4A and the spare row decoder 4B are organized.
The operation of a memory readout in correcting a defective memory cell is now described. Here, it is assumed that the primary word line WL0 of the primary memory cell contains a defective memory cell, and that the word line WL0 is replaced by the spare word line SL0 of the spare memory cell.
When ADDRESS SIGNALS A0 to A1 are fed to the row predecoder 5 as well as to the redundancy-use decision circuit 20, the elements SD0 to SDn of the decision circuit 20 each make a comparison between the addresses of ADDRESS SIGNALS A0 to A1 supplied and their stored addresses of the defective memory cells. For example, if ADDRESS SIGNAL supplied happens to be an address corresponding to the primary word line WL0 of the primary memory cell array 3, this means that the address stored in the element SD0 of the decision circuit 20 agrees with the address of supplied ADDRESS SIGNAL. Then, REDUNDANCY-USE SIGNAL is sent out from the element SD0 of the redundancy-use decision circuit 20. This REDUNDANCY-USE SIGNAL is fed to the primary row decoder 4A as PRIMARY MEMORY STOP SIGNAL 18. Upon receiving STOP SIGNAL 18, the primary row decoder 4A stops operating thereby making the primary word line WL0 non-selective. REDUNDANCY-USE SIGNAL is also supplied to the spare row decoder 4B as REDUNDANCY-SELECTION SIGNAL SWP0 to select the spare word line SW0. This replaces the primary word line WL0 containing the defective memory cell with the spare word line SW0. In this way, the defective memory cell can be corrected.
Next, a conventional semiconductor memory device in which a plurality of memory cells are zoned to form memory cell blocks is described, which is shown in FIG. 11. In accordance with this semiconductor memory device, a memory cell block a (b, c, d) contains a sense amplifier array 1a (1b, 1c, 1d), a spare memory cell array 2a (2b, 2c, 2d), a primary memory cell array 3a (3b, 3c, 3d), a column decoder 6a (6b, 6c, 6d), a primary row decoder 4Aa (4Ab, 4Ac, 4Ad), a redundancy signal generating circuit 20a comprised of elements SDoa to SDna (20b comprised of elements SDob to SDnb, 20c comprised of SDoc to SDnc, and 20d comprised of elements SDod to SDnd), and a row predecoder 5 that is shared among the memory cell blocks. Only one of the memory cell blocks a, b, c, and d is selected by Al - 1,l of supplied ADDRESS SIGNALS A0 to A1 and is brought into operation. The operation of the memory cell blocks a, b, c, and d is the same as the one described in FIG. 8.
Both the conventional semiconductor memory devices of FIG. 9 and FIG. 11, however, require the provision of word lines for every memory cell block. Further, if a defective memory cell is found in a memory cell block, only a spare word line (i.e., a spare memory cell), arranged in the same memory cell block that the defective memory cell is contained, can provide a corrective for the defective memory cell. The size of memory increases with the number of memory cell blocks. This causes the number of spare word lines to increase in a memory chip. As component density per memory chip becomes higher, more complicated fabrication technique is required. Not only the number of spare word lines necessary for a single memory cell block, but also the number of decode lines used to select a spare word line increases. As the number of spare word lines increases, a greater chip area is required.
As the scale of integration becomes larger, the layout pitch of row decoders gets narrower. In order to reduce the pitch, one row decoder is provided for a plurality of word lines, and the word lines are selected by WORD LINE DRIVE SIGNAL, as shown in FIG. 10. In order to drive the spare word lines, the conventional semiconductor memory device additionally requires, besides a primary word line drive signal generation circuit 21A comprised of elements WD0 to WD3, a spare word line drive signal generating circuit 21B comprised of elements SWD0 to SWD3 corresponding to spare word lines SWo0 to SWo3. In this example, however, the spare word line drive signal generating circuit 21B requires four elements (i.e., the elements SWD0 to SWD3), since four spare word lines are provided. The number of spare word lines increases with the scale of integration, which presents a problem that the area of the memory chip disadvantageously increases.